《Table 1 Complexity and maximum clock speed of the EF-DSMs on FPGA》

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《Improved time-interleaved error feedback delta sigma modulator for digital transmitter application》

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The noise transfer function is the same as Eq.（9）.Although the signal transfer function in Eq.（28）is not unit，it is just two clock delays of the original signal x.To evaluate the correctness，the power spectrum density（PSD）simulation of the ITI-EF-DSM for single tone signal input is conducted using Matlab.Single tone full-scale signal with oversampling rate of16 is used as the stimulus.PSD for TI-EF-DSM is also simulated with the same input signal for comparison.The normalized PSDs of the TI-EF-DSM and ITI-EF-DSM are shown in Fig.6.The signals to noise ratios（SNRs）are 50.5 d B and 50.4 d B for the TI-EF-DSM and the ITI-EF-DSM respectively.They are almost the same.The simulation result confirms the correcness of the ITI-EF-DSM.TI-EF-DSM and ITI-EF-DSM are implemented on FPGA.Table 1 lists the synthesized results of three types of EF-DSMs.ITI-EF-DSM consumes largest hardware and gets the highest equivalent processing speed.Although TI-EF-DSM consumes less hardware，it gets lower maximum clock frequency.The non-time-interleaved EF-DSM consumes the least hardware，but the equivalent processing speed is the lowest.