《Table 2.Comparison of device utilization summary.》

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《Berger code based concurrent online self-testing of embedded processors》

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Two versions of the processor（i）standard DLX RISC architecture and（ii）TSC based Self-testable DLX RISC Processor are synthesized and implemented in 7-series Zynq FP-GA（xc7z020clg484-1）.The device utilization reports and overall power consumption for the two designs is summarized in Table 2.The last column in the table shows the hardware/power overhead required for the design（2），which can be traded-off with its ability to facilitate on-line concurrent self-testing.