《Table 2.Performance summary.》
本系列图表出处文件名:随高清版一同展现
《4-port digital isolator based on on-chip transformer》
Here,L is the equivalent inductance of the transformer,which is directly determined by the area of the transformer.C is the parasitic gate capacitance of the cross-coupled NMOS transistor.In order to satisfy the desired oscillation frequency,the on-chip transformer has been designed.In the case that the transformer area is limited to 500μm2,the coil with more turns can gain greater inductance to reduce the switching loss.The on-chip stacked spirals transformer with its center tape connected to Vin is designed by the 3D finite element modeling(FEM)tool.The geometric parameters of the primary and secondary coil of the transformer include outer diameter(Dout),trace width(w),trace separation(s),thickness(t),and turns(N),as shown in Table 1.At 320 MHz,the simulated inductance and quality factor for primary and secondary coils are 216 nH,262 nH,2.1,and 1.1,respectively.
图表编号 | XD00188455100 严禁用于非法目的 |
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绘制时间 | 2018.11.01 |
作者 | Feng Zhang、Ting Zhao、Chunyu Ma、Dongfang Pan |
绘制单位 | University of Science and Technology of China、Institute of Automation, Chinese Academy of Sciences、Institute of Automation, Chinese Academy of Sciences、Institute of Automation, Chinese Academy of Sciences、University of Science and Technology of China |
更多格式 | 高清、无水印(增值服务) |