《Table 1.Instruction formats of DLX RISC》

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《Berger code based concurrent online self-testing of embedded processors》

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During the IF stage，a 32-bit instruction will get fetched from the memory.The PC holds the address of the next instruction to be fetched（i）by incrementing PC by 4 in case of sequential execution and（ii）the branch target address predicted by the branch prediction logic.During the ID stage，the instruction decoder decodes the 32-bit instructions into various fields as given in Table 1 and determines the required operands and branching address.During the EXE stage，the arithmetic logic unit（ALU）performs the arithmetic and logical operations on the operands decoded/provided by the instruction decoder.During the MEM stage，the computed results will be written back to the data memory.The result will be written back into register during the WB stage.The MEM and WB cycles can be performed in a single clock cycle and hence the execution of an instruction can be completed in 4clock cycles.