《计算机体系结构量化研究方法 英文版·第2版》求取 ⇩

1 Fundamentals of Computer Design1

References1

E．1 Implementation Issues for the Snooping Coherence Protocol1

Appendix E:Implementing Coherence Protocols1

D．1 Introduction1

Appendix D:An Alternative to RISC: The Intel 80x861

C．1 Introduction1

Appendix C: Survey of Risc Architectures1

B．1 Why Vector Processors?1

Appendix B:Vector Processors1

A．1 Introduction1

Xerox Paio Alto Research Center1

by DAVID GOLDBERG1

Appendix A: Computer Arithmetic1

Index1

1．1 Introduction1

D．2 80x86 Registers and Data Addressing Modes2

A．2 Basic Techniques of Integer Arithmetic2

C．2 Addressing Modes and Instruction Formats3

1．2 The Task of a Computer Designer3

B．2 Basic Vector Architecture3

C．3 Instructions : The DLX Subset5

E．2 Implementation Issues in the Distributed Directory Protocol6

1．3 Technology and Computer Usage Trends6

D．3 80x86 Integer Operations6

1．4 Cost and Trends in Cost8

D．4 80x86 Floating-Point Operations9

C．4 Instructions : Common Extensions to DLX9

D．5 80x86 Instruction Encoding11

Exercises12

C．5 Instructions Unique to MIPS13

A．3 Floating Point13

B．3 Two Real-World Issues : Vector Length and Stride15

C．6 Instructions Unique to SPARC15

D．6 Putting It All Together : Measurements of Instruction Set Usage15

A．4 Floating-Point Multiplication17

C．7 Instructions Unique to PowerPC18

1．5 Measuring and Reporting Performance18

C．8 Instructions Unique to PA-RISC19

D．7 Concluding Remarks22

B．4 Effectiveness of Compiler Vectorization22

A．5 Floating-Point Addition22

C．9 Concluding Remarks22

B．5 Enhancing Vector Performance23

D．8 Historical Perspective and References23

C．10 References25

A．6 Division and Remainder28

B．6 Putting It All Together : Performance of Vector Processors29

1．6 Quantitative Principles of Computer Design29

A．7More on Floating-Point Arithmetic34

B．7 Fallacies and Pitfalls35

B．8 Concluding Remarks37

A．8 Speeding Up Integer Addition38

B．9 Historical Perspective and References38

1．7 Putting it All Together:The Concept of Memory Hierarchy39

Exercises43

1．8 Fallacies and Pitfalls44

A．9 Speeding Up Integer Multiplication and Division46

1．9 Concluding Remarks51

1．10 Historical Perspective and References53

Exercises60

A．10 Putting It All Together61

A．11 Fallacies and Pit?alls65

A．12 Historical Perspective and References68

2．1 Introduction69

2 Instruction Set Principles and Examples69

2．2 Classifying Instruction Set Architecfures70

Exercises72

2．3 Memory Addressing73

2．4 Operations in the Instruction Set80

2．5 Type and Size of Operands85

2．6 Encoding an Instruction Set87

2．7 Crosscutting Issues:The Role of Compilers89

2．8 Putting it All Together : The DLX Architecture96

2．9 Fallacies and Pitfalls108

2．10 Concluding Remarks111

2．11 Historical Perspective and References112

Exercises118

3．1 What Is Pipelining?125

3 Pipellning125

3．2 The Basic Pipeline for DLX132

3．3 The Major Hurdle of Pipelining ——Pipeline Hazards139

3．4 Data Hazards146

3．5 Control Hazards161

3．6 What Makes Pipelining Hard to Implement?178

3．7 Extending the Dlx Pipeline to Handle Multicycle Operations187

3．8 Crosscutting Issues : Instruction Set Design and Pipelining199

3．9 Putting It All Together: The MIPS R4000 Pipeline201

3．10 Fallacies and Pitfalls209

3．11 Concluding Remarks211

3．12 Historical Perspective and References212

Exercises214

4．1 Instruction-Level Parallelism : Concepts and Challenges221

4 Advanced Pipelining and Instruction-Level Parallelism221

4．2 Overcoming Data Hazards with Dynamic Scheduling240

4．3 Reducing Branch Penalties with Dynamic Hardware Prediction262

4．4 Taking Advantage of More ILP with Multiple Issue278

4．5 Compiler Support for Exploiting ILP289

4．6 Hardware Support for Extracting More Parallelism299

4．7 Studies of ILP317

4．8 Putting It All Together : The PowerPC 620335

4．9 Fallacies and Pitfalls349

4．10 Concluding Remarks352

4．11 Historical Perspective and References354

Exercises362

5．1 Introduction373

5 Memory-Hierarchy Design373

5．2 The ABCs of Caches375

5．3 Reducing Cache Misses390

5．4 Reducing Cache Miss Penalty411

5．5 Reducing Hit Time422

5．6 Main Memory427

5．7 Virtual Memory439

5．8 Protection and Examples of Virtual Memory447

5．9 Crosscutting Issues in the Design of Memory Hierarchies457

5．10 Putting It All Together: The Alpha AXP 21064 Memory Hierarchy461

5．11 Fallacies and Pitfalls466

5．12 Concluding Remarks471

5．13 Historical Perspective and References472

Exercises476

6．1 Introduction485

6 Storage Systems485

6．2 Types of Storage Devices486

6．3 Buses-Connecting I/O Devices to CPU/Memory496

6．4 I/O Performance Measures504

6．5 Reliability, Availability, and RAID521

6．6 Crosscutting Issues : Interfacing to an Operating System525

6．7 Designing an I/O System528

6．8 Putting It All Together: UNIX File System Performance539

6．9 Fallacies and Pitfalls548

6．10 Concluding Remarks553

6．11Historical Perspective and References553

Exercises557

7 Interconnection Networks563

7．1 Introduction563

7．2 A Simple Network565

7．3 Connecting the Interconnection Network to the Computer573

7．4 Interconnection Network Media576

7．5 Connecting More Than Two Computers579

7．6 Practical Issues for Commercial Interconnection Networks597

7．7 Examples of Interconnection Networks601

7．8 Crosscutting Issues for Interconnection Networks605

7．9 Intemetworking608

7．10 Putting It All TOgether : An ATM Network of Workstations613

7．11 Fallacies and Pitfalls622

7．12 Concluding Remarks625

7．13 Historical Perspective and References626

Exercises629

8 Multiprocessors635

8．1 Introduction635

8．2 Characteristics of Application Domains647

8．3 Centralized Shared-Memory Architectures654

8．4 Distributed Shared-Memory Architectures677

8．5 Synchronization694

8．6 Models of Memory Consistency708

8．7 Crosscutting Issues721

8．8 Putting It All Together : The SGI Challenge Multiprocessor728

8．9 Fallacies and Pitfalls734

8．10 Concluding Remarks740

8．11 Historical Perspective and References745

Exercises755