《IBM CPU AND STORAGE ARCHITECTURE》求取 ⇩

ContentsIntroduction5

How to Use This Book6

Section One IBM LARGE-SCALE PROCESSORSChapter 1 Processor Evolution and System Structure3

Lesson 1.1 IBM Large-Scale Processor Evolution4

Computing System Architecture4

Early Processors5

System/360 Processors5

System/370 Processors7

System/370 Architectural Extensions8

3030 Processors8

4300 Processors8

3080 Processors9

System/370 Extended Architecture9

Plug-Compatible Equipment10

IBM Personal Computer10

Lesson 1.2 Architecture Design Objectives13

Computing System Goals13

Productivity13

Access to Information14

Growth14

Reliability14

Large-Scale Processor Design Objectives14

Modularity and Expandability14

Application Flexibility15

I/O Device Flexibility15

Compatibility15

Programming System Flexibility16

Reliability,Availability,and Serviceability16

Lesson 1.3 Computing System Structure18

Central Processing Unit Structure18

CPU Components18

CPU Operation19

Program-Status Word20

Registers20

Main Storage Structure20

Storage Addressing21

Boundary Alignment21

Bits and Half-Bytes23

Section Two MAIN STORAGEChapter 2 Data Formats31

Lesson 2.1 Binary and Character Data32

Fixed-Point Binary Data32

Fixed-Point Arithmetic33

The Sign Bit33

Fullword and Halfword Numbers33

Positive Fixed-Point Numbers34

Negative Fixed-Point Numbers34

Two's Complement Notation34

Two's Complement Example35

Two's Complement Addition35

Loading 16-Bit Negative Numbers35

Binary Arithmetic Instructions36

Binary Logical Data36

Character Data37

The BCD Coding Scheme37

The EBCDIC Coding Scheme37

The ASCII Coding Scheme39

Zoned-Decimal Data39

Lesson 2.2 Packed-Decimal and Floating-Point Data42

Packed-Decimal Data42

Packed-Decimal Sign Information42

Converting to Packed and Binary43

Packed-Decimal Arithmetic44

Floating-Point Data45

Scientific Notation45

Floating-Point Numbers45

Floating-Point Data Variations46

Chapter 3 Main Storage Organization55

Lesson 3.1 Virtual Storage56

Virtual Storage56

Virtual Storage Implementation56

Dynamic Real Storage Assignment57

Transparent Operation57

Virtual and Transparent58

Virtual Storage Size58

Virtual Storage Operating Systems58

DOS/VSE and OS/VS1 Virtual Storage Management58

MVS Virtual Storage Management59

MVS/XA Virtual Storage Management60

Virtual Storage Use61

Addressing Modes61

System/360 Addressing61

System/370 Addressing62

Extended Addressing62

System/370 Extended Architecture63

Lesson 3.2 Real Storage66

Fixed Main Storage Locations66

Assigned Main Storage Locations67

Addresses of the Assigned Locations67

Assigned Location Functions67

Program-Status Word Locations68

Interrupts68

Old PSW Locations69

New PSW Locations69

Assigned Locations for I/O Processing70

System/370 I/O Operations70

370/XA I/O Operations71

Section Three CENTRAL PROCESSING UNITChapter 4 Machine Instructions79

Lesson 4.1 Instruction Operands80

Assembler Language Instructions80

Assembler Listing81

Operand Types82

Register Operands82

The Load Register(LR)Instruction83

Storage Operands83

Add(A)Instruction83

Base/Displacement Addressing84

Base/Displacement Address Format84

Assembler Listing85

Base Register Loading86

Storage Address Calculation86

Self-Relocation87

Index Registers88

Immediate Operands89

Move(immediate)(MVI)Instruction89

Lesson 4.2 Instruction Formats93

Machine Instruction Formats93

RR-Format Instructions94

RRE-Format Instructions95

RX-Format Instructions95

RS-Format Instructions96

SI-Format Instructions97

S-Format Instructions98

SS-Format Instructions98

Single Operand Length99

Two Operand Lengths99

Register SDecifications100

SSE-Format Instructions100

Lesson 4.3 Instruction Functions104

Instruction Categories104

Expanded Functional Categories105

Fixed-Point Arithmetic Instructions105

Logical Instructions106

The AND Operation107

The OR Operation107

The EXCLUSIVE-OR Operation107

The Mask107

General Register Shifting Instructions108

General Register Load and Store Instructions108

Data Moving,Conversion,and Translation Instructions109

Decimal Instructions110

Floating-Point Instructions110

Special-Purpose Control Instructions112

Privileged I/O Instructions112

Privileged System-Control Instructions113

Lesson 4.4 Compare and Branch Instructions117

Compare Instructions117

The PSW Condition-Code Bits118

Condition-Code Setting118

Branch Instructions119

Testing for Operands Equal120

Testing for First Operand Low120

Testing for First Operand High120

Testing for Multiple Values120

Extended Mnemonics121

Chapter 5 CPU Operation127

Lesson 5.1 Instruction Execution128

Processor Structure128

Program-Status Word(PSW)129

EC-Mode PSW129

XA-Mode PSW130

BC-Mode PSW130

Next Instruction Address130

Instruction Execution Cycle130

Add Instruction Execution130

Locating the Instruction131

Updating the PSW132

Calculating the Storage Operand Address132

Performing the Addition133

Repeating the Cycle134

Compare and Branch Instructions134

Compare Instruction Execution135

Branch Instruction Execution135

Conceptual Sequence135

Lesson 5.2 The Interrupt System139

Interrupt Processing139

The Six Interrupt Types139

Input/Output Interruption140

External Interruption140

Program Interruption140

Supervisor-Call Interruption140

Machine-Check Interruption140

Restart Interruption140

Assigned PSW Locations141

A Machine-Check Interruption141

PSW Storing and Loading142

Interrupt Handler Operation142

Other Interrupt Types142

CPU State Alternatives143

Wait or Running State143

Stopped or Operating State143

Problem or Supervisor State144

PSW State Alternative Bits144

Chapter 6 CPU Features151

Lesson 6.1 General CPU Features152

Storage Protection152

The Access-Control Bits153

The Fetch-Protection Bit153

The Reference and Change Bits153

Software Storage Protection154

Compatibility Features154

The Direct Control Feature154

Dynamic Address Translation154

The Monitoring Feature155

Program Event Recording155

Main Storage Performance156

Access Width156

Cycle Time156

Storage Interleaving156

High-Speed Buffer156

Lesson 6.2 Multiprocessing Concepts160

Loosely Coupled Multiprocessing160

No Direct Connection160

Sharing SPOOL Devices161

Connecting Processors Together162

Loosely Coupled Multiprocessing Differences163

Tightly Coupled Multiprocessing163

Attached Processors164

True Tightly Coupled Multiprocessing164

Lesson 6.3 Multiprocessing Hardware Features167

Assigned Main Storage Locations167

Absolute Main Storage168

Real Main Storage168

The Prefixing Feature169

Prefixing Example 1169

Prefixing Example 2170

Prefixing Example 3170

Other Multiprocessing Hardware Features171

Lesson 6.4 Timing and Clock Features174

Time-of-Day Clock174

Clock Comparator175

CPU Timer176

Interval Timer177

Index181