《DIGITAL INTEGRATED CIRCUITS》

Part 1The Fabrics1

Chapter 1Introduction3

1.1 A Historical Perspective4

1.2 Issues in Digital Integrated Circuit Design6

1.3Quality Metrics of a Digital Design15

1.3.1 Cost of an Integrated Circuit16

1.3.2 Functionality and Robustness18

1.3.3 Performance27

1.3.4 Power and Energy Consumption30

1.4 Summary31

1.5To Probe Further31

Reference Books32

References33

Chapter 2The Manufacturing Process35

2.1 Introduction36

2.2Manufacturing CMOS Integrated Circuits36

2.2.1 The Silicon Wafer37

2.2.2 Photolithography37

2.2.3 Some Recurring Process Steps41

2.2.4 Simplified CMOS Process Flow42

2.3 Design Rules—The Contract between Designer and Process Engineer47

2.4Packaging Integrated Circuits51

2.4.1 Package Materials52

2.4.2 Interconnect Levels53

2.4.3 Thermal Considerations in Packaging59

2.5Perspective—Trends in Process Technology61

2.5.1 Short-Term Developments61

2.5.2 In the Longer Term63

2.6 Summary64

2.7To Probe Further64

References64

Design Methodology Insert AIC LAYOUT67

A.1To Probe Further71

References71

Chapter 3The Devices73

3.1 Introduction74

3.2The Diode74

3.2.1 A First Glance at the Diode—The Depletion Region75

3.2.2 Static Behavior77

3.2.3 Dynamic，or Transient，Behavior80

3.2.4 The Actual Diode—Secondary Effects84

3.2.5 The SPICE Diode Model85

3.3The MOS（FET） Transistor87

3.3.1 A First Glance at the Device87

3.3.2 The MOS Transistor under Static Conditions88

3.3.3 The Actual MOS Transistor—Some Secondary Effects114

3.3.4 SPICE Models for the MOS Transistor117

3.4 A Word on Process Variations120

3.5 Perspective—Technology Scaling122

3.6 Summary128

3.7To Probe Further129

References130

Design Methodology Insert BCircuit Simulation131

References134

Chapter 4The Wire135

4.1 Introduction136

4.2 A First Glance136

4.3Interconnect Parameters—Capacitance，Resistance，and Inductance138

4.3.1 Capacitance138

4.3.2 Resistance144

4.3.3 Inductance148

4.4Electrical Wire Models150

4.4.1 The Ideal wire151

4.4.2 The Lumped Model151

4.4.3 The Lumped RC Model152

4.4.4 The Distributed rc Line156

4.4.5 The Transmission Line159

4.5SPICE Wire Models170

4.5.1 Distributed rc Lines in SPICE170

4.5.2 Transmission Line Models in SPICE170

4.5.3 Perspective：A Look into the Future171

4.6Summary174

4.7To Probe Further174

References174

Part 2A Circuit Perspective177

Chapter 5The CMOS Inverter179

5.1 Introduction180

5.2 The Static CMOS Inverter—An Intuitive Perspective180

5.3Evaluating the Robustness of the CMOS Inverter：The Static Behavior184

5.3.1 Switching Threshold185

5.3.2 Noise Margins188

5.3.3 Robustness Revisited191

5.4Performance of CMOS Inverter：The Dynamic Behavior193

5.4.1 Computing the Capacitances194

5.4.2 Propagation Delay：First-Order Analysis199

5.4.3 Propagation Delay from a Design Perspective203

5.5Power，Energy，and Energy Delay213

5.5.1 Dynamic Power Consumption214

5.5.2 Static Consumption223

5.5.3 Putting It All Together225

5.5.4 Analyzing Power Consumption Using SPICE227

5.6 Perspective：Technology Scaling and its Impact on the Inverter Metrics229

5.7 Summary232

5.8To Probe Further233

References233

Chapter 6Designing Combinational Logic Gates in CMOS235

6.1 Introduction236

6.2Static CMOS Design236

6.2.1 Complementary CMOS237

6.2.2 Ratioed Logic263

6.2.3 Pass-Transistor Logic269

6.3Dynamic CMOS Design284

6.3.1 Dynamic Logic：Basic Principles284

6.3.2 Speed and Power Dissipation of Dynamic Logic287

6.3.3 Signal Integrity Issues in Dynamic Design290

6.3.4 Cascading Dynamic Gates295

6.4Perspectives303

6.4.1 How to Choose a Logic Style？303

6.4.2 Designing Logic for Reduced Supply Voltages303

6.5 Summary306

6.6To Probe Further307

References308

Design Methodology Insert CHow to Simulate Complex Logic Circuits309

C.1 Representing Digital Data as a Continuous Entity310

C.2 Representing Data as a Discrete Entity310

C.3Using Higher-Level Data Models315

References317

Design Methodology Insert D Layout Techniques for Complex Gates319

Chapter 7Designing Sequential Logic Circuits325

7.1Introduction326

7.1.1 Timing Metrics for Sequential Circuits327

7.1.2 Classification of Memory Elements328

7.2Static Latches and Registers330

7.2.1 The Bistability Principle330

7.2.2 Multiplexer-Based Latches332

7.2.3 Master-Slave Edge-Triggered Register333

7.2.4 Low-Voltage Static Latches339

7.2.5 Static SR Flip-Flops—Writing Data by Pure Force341

7.3Dynamic Latches and Registers344

7.3.1 Dynamic Transmission-Gate Edge-triggered Registers344

7.3.2 C 2MOS—A Clock-Skew Insensitive Approach346

7.3.3 True Single-Phase Clocked Register （TSPCR）350

7.4Alternative Register Styles354

7.4.1 Pulse Registers354

7.4.2 Sense-Amplifier-Based Registers356

7.5Pipelining：An Approach to Optimize Sequential Circuits358

7.5.1 Latch- versus Register-Based Pipelines360

7.5.2 NORA-CMOS—A Logic Style for Pipelined Structures361

7.6Nonbistable Sequential Circuits364

7.6.1 The Schmitt Trigger364

7.6.2 Monostable Sequential Circuits367

7.6.3 Astable Circuits368

7.7 Perspective：Choosing a Clocking Strategy370

7.8 Summary371

7.9To Probe Further372

References372

Part 3A System Perspective375

Chapter 8Implementation Strategies for Digital ICS377

8.1 Introduction378

8.2 From Custom to Semicustom and Structured-Array Design Approaches382

8.3 Custom Circuit Design383

8.4Cell-Based Design Methodology384

8.4.1 Standard Cell385

8.4.2 Compiled Cells390

8.4.3 Macrocells，Megacells and Intellectual Property392

8.4.4 Semicustom Design Flow396

8.5Array-Based Implementation Approaches399

8.5.1 Prediffused （or Mask-Programmable） Arrays399

8.5.2 Prewired Arrays404

8.6 Perspective—The Implementation Platform of the Future420

8.7 Summary423

8.8To Probe Further423

References424

Design Methodology Insert ECharacterizing Logic and Sequential Cells427

References434

Design Methodology Insert FDesign Synthesis435

References443

Chapter 9Coping with Interconnect445

9.1 Introduction446

9.2Capacitive Parasitics446

9.2.1 Capacitance and Reliability—Cross Talk446

9.2.2 Capacitance and Performance in CMOS449

9.3Resistive Parasitics460

9.3.1 Resistance and Reliability—Ohmic Voltage Drop460

9.3.2 Electromigration462

9.3.3 Resistance and Performance—RC Delay464

9.4Inductive Parasitics469

9.4.1 Inductance and Reliability— Voltage Drop469

9.4.2 Inductance and Performance—Transmission-line Effects475

9.5Advanced Interconnect Techniques480

9.5.1 Reduced-Swing Circuits480

9.5.2 Current-Mode Transmission Techniques486

9.6 Perspective：Networks-on-a-Chip487

9.7 Summary488

9.8To Probe Further489

References489

Chapter 10 Timing Issues in Digital Circuits491

10.1Introduction492

10.2Timing Classification of Digital Systems492

10.2.1 Synchronous Interconnect492

10.2.2 Mesochronous interconnect493

10.2.3 Plesiochronous interconnect493

10.2.4 Asynchronous Interconnect494

10.3Synchronous Design—An In-depth Perspective495

10.3.1 Synchronous Timing Basics495

10.3.2 Sources of Skew and Jitter502

10.3.3 Clock-Distribution Techniques508

10.3.4 Latch-Based Clocking516

10.4Self-Timed Circuit Design519

10.4.1 Self-Timed Logic—An Asynchronous Technique519

10.4.2 Completion-Signal Generation522

10.4.3 Self-Timed Signaling526

10.4.4 Practical Examples of Self-Timed Logic531

10.5Synchronizers and Arbiters534

10.5.1 Synchronizers—Concept and Implementation534

10.5.2 Arbiters538

10.6Clock Synthesis and Synchronization Using a Phase-Locked Loop539

10.6.1 Basic Concept540

10.6.2 Building Blocks of a PLL542

10.7Future Directions and Perspectives546

10.7.1 Distributed Clocking Using DLLs546

10.7.2 Optical Clock Distribution548

10.7.3 Synchronous versus Asynchronous Design549

10.8 Summary550

10.9To Probe Further551

References551

Design Methodology Insert GDesign Verification553

References557

Chapter 11 Designing Arithmetic Building Blocks559

11.1Introduction560

11.2 Datapaths in Digital Processor Architectures560

11.3The Adder561

11.3.1 The Binary Adder：Definitions561

11.3.2 The Full Adder：Circuit Design Considerations564

11.3.3 The Binary Adder：Logic Design Considerations571

11.4 The Multiplier586

11.4.1 The Multiplier：Definitions586

11.4.2 Partial-Product Generation587

11.4.3 Partial-Product Accumulation589

11.4.4 Final Addition593

11.4.5 Multiplier Summary594

11.5The Shifter594

11.5.1 Barrel Shifter595

11.5.2 Logarithmic Shifter596

11.6 Other Arithmetic Operators596

11.7Power and Speed Trade-offs in Datapath Structures600

11.7.1 Design Time Power-Reduction Techniques601

11.7.2 Run-Time Power Management611

11.7.3 Reducing the Power in Standby （or Sleep） Mode617

11.8 Perspective：Design as a Trade-off618

11.9 Summary619

11.10 To Probe Further620

References621

Chapter 12 Designing Memory and Array Structures623

12.1Introduction624

12.1.1 Memory Classification625

12.1.2 Memory Architectures and Building Blocks627

12.2The Memory Core634

12.2.1 Read-Only Memories634

12.2.2 Nonvolatile Read-Write Memories647

12.2.3 Read-Write Memories （RAM）657

12.2.4 Contents-Addressable or Associative Memory （CAM）670

12.3Memory Peripheral Circuitry672

12.3.1 The Address Decoders672

12.3.2 Sense Amplifiers679

12.3.3 Voltage References686

12.3.4 Drivers/Buffers689

12.3.5 Timing and Control689

12.4Memory Reliability and Yield693

12.4.1 Signal-to-Noise Ratio693

12.4.2 Memory Yield698

12.5Power Dissipation in Memories701

12.5.1 Sources of Power Dissipation in Memories701

12.5.2 Partitioning of the Memory702

12.5.3 Addressing the Active Power Dissipation702

12.5.4 Data-Retention Dissipation704

12.5.5 Summary707

12.6Case Studies in Memory Design707

12.6.1 The Programmable Logic Array （PLA）707

12.6.2 A 4-Mbit SRAM710

12.6.3 A 1-Gbit NAND Flash Memory712

12.7 Perspective：Semiconductor Memory Trends and Evolutions714

12.8 Summary716

12.9To Probe Further717

References718

Design Methodology Insert HValidation and Test of Manufactured Circuits721

H.1 Introduction721

H.2 Test Procedure722

H.3Design for Testability723

H.3.1 Issues in Design for Testability723

H.3.2 Ad Hoc Testing725

H.3.3 Scan-Based Test726

H.3.4 Boundary-Scan Design729

H.3.5 Built-in Self-Test （BIST）730

H.4Test-Pattern Generation734

H.4.1 Fault Models734

H.4.2 Automatic Test-Pattern Generation （ATPG）736

H.4.3 Fault Simulation737

H.5To Probe Further737

References737

Problem Solutions739

Index745