《Tab.2 Parameters for ITC'02 benchmarks》

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《三维集成电路绑定中测试成本缩减的优化堆叠顺序（英文）》

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We develop our experimental program via C++and run the benchmarks on a 3.40 GHz Intel i7 processor w ith16 GB RAM.All the programs are finished w ithin only a few seconds.In order to demonstrate our optimization scheme，w e use ITC02 benchmark So Cs[9]to realize our experiments as depicted in Tab.2.As most of the benchmark circuits only have the test length information，w e assume other information such as area and pow er.We use the estimation method proposed in Ref.[10].The area of each core is computed by the summation of input pins，output pins，and scan cells，multiplied by an area density of 3.18×10-4mm2/number，w hich is obtained by the average synthesis results of TSM C 180 nm technology.The test pow er is computed by the pow er density of 1.4m W/mm2，multiplied by the core area.